1. Field of the Invention
The present invention relates to a semiconductor device having an SOI structure.
2. Description of the Background Art
Referring to FIG. 102, a background art semiconductor device having an SOI structure comprised of a silicon substrate 1, a buried oxide film 2 and an SOI (Silicon On Insulator) layer 3 has been constructed such that a full oxide film 32 completely isolates transistor formation regions in the SOI layer 3 from each other. For example, a single NMOS transistor formed in an NMOS transistor formation region has been completely isolated from other transistors by the full oxide film 32. In the semiconductor device shown in FIG. 102, an interlayer insulation film 4 covers the SOI layer 3.
As shown in FIG. 102, the single NMOS transistor completely isolated from other transistors by the full oxide film 32 comprises a drain region 5, a source region 6 and a channel formation region 7 which are formed in the SOI layer 3, a gate oxide film 8 formed on the channel formation region 7, and a gate electrode 9 formed on the gate oxide film 8. An interconnect layer 22 formed on the interlayer insulation film 4 is electrically connected through a contact 21 formed in the interlayer insulation film 4 to the drain region 5 or the source region 6.
Thus, the background art semiconductor device having the SOI structure in which devices (transistors) are completely isolated from each other in the SOI layer is constructed to provide complete isolation between PMOS and NMOS transistors to prevent latchup in principle.
Therefore, the manufacture of a semiconductor device having the SOI structure and including CMOS transistors has been advantageous in that a minimum isolation width determined by the micromachining technique may be used to reduce the area of a chip. Such a semiconductor device having the SOI structure, however, presents various drawbacks resulting from a so-called floating-substrate effect, such as a kink effect caused by carriers (holes for an NMOS transistor) generated by impact ionization and stored in the channel formation region, the degradation in operation breakdown voltage, and the frequency-dependence of delay time due to the unstabilized electric potential of the channel formation region.